CPC G11C 13/0069 (2013.01) [G11C 13/003 (2013.01); G11C 2013/0078 (2013.01); G11C 2213/15 (2013.01); G11C 2213/73 (2013.01)] | 18 Claims |
1. An apparatus, comprising:
a memory having a plurality of memory cells; and
circuitry configured to program a memory cell of the plurality of memory cells to one of two possible data states by:
applying a first voltage pulse to the memory cell, wherein:
the first voltage pulse has a negative polarity; and
the first voltage pulse has a first magnitude; and
applying a second voltage pulse to the memory cell, wherein:
the second voltage pulse has a positive polarity; and
the second voltage pulse has a second magnitude; and
wherein the one of the two possible data states to which the memory cell is being programmed is in the negative polarity direction.
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