US 11,887,664 B2
Systems and methods for adaptive self-referenced reads of memory devices
Graziano Mirichigni, Vimercate (IT); and Corrado Villa, Sovico (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 12, 2022, as Appl. No. 18/079,515.
Application 18/079,515 is a continuation of application No. 17/364,067, filed on Jun. 30, 2021, granted, now 11,538,522.
Prior Publication US 2023/0109794 A1, Apr. 13, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/14 (2006.01); G11C 16/28 (2006.01); G11C 13/00 (2006.01)
CPC G11C 13/004 (2013.01) [G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 2013/0045 (2013.01)] 20 Claims
OG exemplary drawing
 
16. A memory device, comprising:
a memory array comprising a plurality of memory cells;
a control circuit operatively coupled to the memory array, the control circuit configured to:
apply a first voltage to the memory array in response to receiving a read request;
count a total number of the plurality of memory cells that have switched to an active read state based on the first voltage;
use a lookup table (LUT) to determine if the total number falls inside of an approach range of values, a final step range of values, or a combination thereof; and
apply one or more voltage steps if the total number is inside of the approach range of values and apply a single voltage step if the total number is inside of the final step range of values to return data.