CPC G11C 13/004 (2013.01) [G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 2013/0045 (2013.01)] | 20 Claims |
16. A memory device, comprising:
a memory array comprising a plurality of memory cells;
a control circuit operatively coupled to the memory array, the control circuit configured to:
apply a first voltage to the memory array in response to receiving a read request;
count a total number of the plurality of memory cells that have switched to an active read state based on the first voltage;
use a lookup table (LUT) to determine if the total number falls inside of an approach range of values, a final step range of values, or a combination thereof; and
apply one or more voltage steps if the total number is inside of the approach range of values and apply a single voltage step if the total number is inside of the final step range of values to return data.
|