CPC G11C 13/004 (2013.01) [G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 2013/0045 (2013.01)] | 20 Claims |
1. A memory device, comprising:
a memory array comprising a plurality of memory cells;
a control circuit operatively coupled to the memory array, the control circuit configured to:
apply a first voltage having a first voltage duration to the memory array in response to receiving a read request;
count a number of the plurality of memory cells that have switched to an active read state based on the first voltage;
derive a second voltage duration based on the number; and
apply a second voltage having the second voltage duration to the memory array.
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