US 11,887,663 B2
Systems and methods for adaptive self-referenced reads of memory devices
Graziano Mirichigni, Vimercate (IT); Riccardo Muzzetto, Arcore (IT); and Ferdinando Bedeschi, Biassono (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 12, 2022, as Appl. No. 18/079,494.
Application 18/079,494 is a continuation of application No. 17/364,029, filed on Jun. 30, 2021, granted, now 11,562,790.
Prior Publication US 2023/0104012 A1, Apr. 6, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/22 (2006.01); G11C 13/00 (2006.01)
CPC G11C 13/004 (2013.01) [G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 2013/0045 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory array comprising a plurality of memory cells;
a control circuit operatively coupled to the memory array, the control circuit configured to:
apply a first voltage having a first voltage duration to the memory array in response to receiving a read request;
count a number of the plurality of memory cells that have switched to an active read state based on the first voltage;
derive a second voltage duration based on the number; and
apply a second voltage having the second voltage duration to the memory array.