US 11,887,660 B2
Time-interleaving sensing scheme for pseudo dual-port memory
Yi-Ping Kuo, Hsinchu (TW); and Yi-Te Chiu, Hsinchu (TW)
Assigned to MEDIATEK INC., Hsin-Chu (TW)
Filed by MEDIATEK INC., Hsin-Chu (TW)
Filed on Aug. 24, 2022, as Appl. No. 17/894,191.
Application 17/894,191 is a division of application No. 17/210,521, filed on Mar. 24, 2021, granted, now 11,676,657.
Claims priority of provisional application 63/010,715, filed on Apr. 16, 2020.
Prior Publication US 2022/0406373 A1, Dec. 22, 2022
Int. Cl. G11C 11/419 (2006.01)
CPC G11C 11/419 (2013.01) 8 Claims
OG exemplary drawing
 
1. A pseudo dual-port memory, comprising:
a single-port memory;
a multiplexer, configured to receive a first address and a second address, and output one of the first address and the second address to the single-port memory;
a timing control circuit, configured to generate a multiplexer control signal to control the multiplexer to sequentially output the first address and the second address to the single-port memory; and
an output circuit, configured to receive output data from the single-port memory to generate a first reading result corresponding to the first address and a second reading result corresponding to the second address; and the output circuit comprises:
a first sense amplifier, configured to receive the output data from the single-port memory to generate first data to a first latch according to a first control signal, wherein the first data stored in the first latch serves as the first reading result; and
a second sense amplifier, configured to receive the output data from the single-port memory to generate second data to a second latch according to a second control signal, wherein the second data stored in the second latch serves as the second reading result;
wherein the timing control circuit generates the multiplexer control signal to control the multiplexer to sequentially output the first address and the second address to the single-port memory within a clock cycle, and the timing control circuit further generates the first control signal and the second control signal to sequentially enable the first sense amplifier and the second sense amplifier.