US 11,887,659 B2
Apparatuses and methods for driving data lines in memory arrays
Yuhei Takahashi, Kanagawa (JP); and Minari Arai, Saitama (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Jul. 2, 2020, as Appl. No. 16/919,453.
Prior Publication US 2022/0005522 A1, Jan. 6, 2022
Int. Cl. G11C 11/4096 (2006.01); G11C 11/4091 (2006.01); G11C 11/408 (2006.01)
CPC G11C 11/4096 (2013.01) [G11C 11/4091 (2013.01); G11C 11/4087 (2013.01)] 11 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory array comprising a plurality of banks, wherein each bank of the plurality of banks includes a plurality of mats each including a respective first mat;
a first plurality of main data lines each coupled to at least a first subset of the plurality of banks and each of the first plurality of main data lines configured to receive read data and provide write data to the first subset of the plurality of banks, wherein the first plurality of main data lines includes a first main data line;
a second plurality of main data lines each coupled to a second subset of the plurality of banks and each of the second plurality of main data lines configured to provide write data to the second subset of the plurality of banks, wherein a length of the second plurality of main data lines is less than a length of the first plurality of main data lines, wherein each of the first plurality of main data lines are further coupled to the second subset of the plurality of banks and each of the first plurality of main data lines are further configured to receive read data from the second subset of the plurality of banks,. wherein the second plurality of main data lines includes a second main data line, wherein the first main data line is configured to write data only to the respective first mats of the first subset of the plurality of banks, and wherein the second main data line is configured to write data only to the respective first mats of the second subset of the plurality of banks:
a plurality of local data lines;
a plurality of sub-amplifiers coupled between the plurality of local data lines and the first plurality of main data lines and the second plurality of main data lines;
a plurality of bit lines coupled to memory cells of the memory array;
a plurality of sense amplifiers coupled between the local data lines and the bit lines;
a global data bus coupled to the first plurality of main data lines and the second plurality of main data lines; and
an input/output circuit coupled to the global data bus.