US 11,887,655 B2
Sense amplifier, memory, and method for controlling sense amplifier by configuring structures using switches
Wenjuan Lu, Hefei (CN); Junlin Ge, Hefei (CN); Jun He, Hefei (CN); Zhan Ying, Hefei (CN); Xin Li, Hefei (CN); Kanyu Cao, Hefei (CN); Chunyu Peng, Hefei (CN); Zhiting Lin, Hefei (CN); Xiulong Wu, Hefei (CN); and Junning Chen, Hefei (CN)
Assigned to ANHUI UNIVERSITY, Anhui (CN); and CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by ANHUI UNIVERSITY, Anhui (CN); and CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 14, 2021, as Appl. No. 17/474,172.
Application 17/474,172 is a continuation of application No. PCT/CN2020/139627, filed on Dec. 25, 2020.
Claims priority of application No. 202010811719.9 (CN), filed on Aug. 13, 2020.
Prior Publication US 2022/0051713 A1, Feb. 17, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/4091 (2006.01); G11C 11/4096 (2006.01); G11C 11/4094 (2006.01)
CPC G11C 11/4091 (2013.01) [G11C 11/4094 (2013.01); G11C 11/4096 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A sense amplifier, comprising:
an amplification circuit arranged to read a data in a memory cell on a first bit line or a second bit line; and
a control circuit, electrically connected to the amplification circuit;
wherein in a case of reading the data in the memory cell on the first bit line, at an offset compensation stage of the sense amplifier, the control circuit is arranged to configure the amplification circuit to comprise a first diode structure, a first current mirror structure, and a first inverter with an input terminal and an output terminal connected to each other;
in a case of reading the data in the memory cell on the second bit line, at the offset compensation stage of the sense amplifier, the control circuit is arranged to configure the amplification circuit to comprise a second diode structure, a second current mirror structure, and a second inverter with an input terminal and an output terminal connected to each other.