US 11,887,654 B2
Vertical memory device
Seung-Hwan Kim, Seoul (KR); Su-Ock Chung, Seoul (KR); and Seon-Yong Cha, Chungcheongbuk-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on May 9, 2022, as Appl. No. 17/739,944.
Application 17/739,944 is a continuation of application No. 16/854,382, filed on Apr. 21, 2020, granted, now 11,355,177.
Claims priority of application No. 10-2019-0084689 (KR), filed on Jul. 12, 2019.
Prior Publication US 2022/0262425 A1, Aug. 18, 2022
Int. Cl. G11C 7/10 (2006.01); G11C 11/408 (2006.01); H01L 49/02 (2006.01); H01L 23/528 (2006.01); H10B 12/00 (2023.01)
CPC G11C 11/4085 (2013.01) [H01L 23/528 (2013.01); H01L 28/86 (2013.01); H10B 12/30 (2023.02); H10B 12/50 (2023.02)] 11 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a peripheral circuit portion including a sub word line driver circuit;
a bit line oriented vertically over the peripheral circuit portion;
a capacitor positioned over the peripheral circuit portion; and
an active layer oriented laterally between the bit line and the capacitor; and
a word line extending along a direction intersecting the active layer,
wherein the sub word line driver circuit is positioned underneath the end of the word line.