CPC G11C 11/4085 (2013.01) [H01L 23/528 (2013.01); H01L 28/86 (2013.01); H10B 12/30 (2023.02); H10B 12/50 (2023.02)] | 11 Claims |
1. A memory device, comprising:
a peripheral circuit portion including a sub word line driver circuit;
a bit line oriented vertically over the peripheral circuit portion;
a capacitor positioned over the peripheral circuit portion; and
an active layer oriented laterally between the bit line and the capacitor; and
a word line extending along a direction intersecting the active layer,
wherein the sub word line driver circuit is positioned underneath the end of the word line.
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