US 11,887,646 B2
Capacitor structure and method of forming the same
Liang Chen, Wuhan (CN); Cheng Gan, Wuhan (CN); Xin Wu, Wuhan (CN); and Wei Liu, Wuhan (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Wuhan (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed on Nov. 8, 2021, as Appl. No. 17/453,919.
Application 17/453,919 is a division of application No. 16/367,298, filed on Mar. 28, 2019, granted, now 11,232,825.
Application 16/367,298 is a continuation of application No. PCT/CN2019/075366, filed on Feb. 18, 2019.
Prior Publication US 2022/0059152 A1, Feb. 24, 2022
Int. Cl. G11C 11/24 (2006.01); G11C 11/404 (2006.01); H01L 49/02 (2006.01); H10B 12/00 (2023.01)
CPC G11C 11/24 (2013.01) [G11C 11/404 (2013.01); H01L 28/40 (2013.01); H10B 12/395 (2023.02)] 20 Claims
OG exemplary drawing
 
13. A method for manufacturing an integrated circuit chip, comprising:
forming a doped region in a substrate from a first main surface, the substrate having an opposing second main surface;
forming a transistor at a first location of the first main surface of the substrate; and
forming a capacitor at a second location of the substrate, the capacitor comprising:
a first conductive line and a second conductive line that are formed from the doped region of the substrate and extends from the first main surface to the second main surface of the substrate;
an insulating structure that is formed between the first and second conductive lines and extends from the first main surface to the second main surface; and
contacts formed in a dielectric layer and arranged along the first and second conductive lines, the dielectric layer being formed over the first main surface of the substrate, the contacts extending through the dielectric layer and into the first and second conductive lines.