| CPC G09G 3/3258 (2013.01) [G09G 3/3266 (2013.01); G09G 3/3291 (2013.01); G09G 3/3275 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/027 (2013.01); G09G 2310/0264 (2013.01); G09G 2310/0278 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01)] | 10 Claims |
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1. A pixel circuit, comprising:
a capacitor connected between a first node and a second node;
a driving element comprising a gate electrode connected to the second node, a first electrode to which a pixel driving voltage is applied, and a second electrode connected to a third node;
a light-emitting element comprising an anode electrode connected to a fourth node and a cathode electrode to which a low-potential power supply voltage is applied;
a first switch element configured to be turned on by a gate-on voltage of a first scan pulse to apply a data voltage to the first node;
a second switch element configured to be turned on by a gate-on voltage of a second scan pulse to connect the second node to the third node;
a third switch element configured to be turned on by a gate-on voltage of a first light-emitting control pulse to apply a reference voltage to the first node, the reference voltage being lower than the pixel driving voltage and the low-potential power supply voltage;
a fourth switch element configured to be turned on by the gate-on voltage of a second light-emitting control pulse to connect the third node to the fourth node; and
a fifth switch element configured to be turned on by the gate-on voltage of the second scan pulse to apply the reference voltage to the fourth node,
wherein:
a driving period of the pixel circuit includes a first step, a second step, a third step, a fourth step, and a fifth step,
the first scan pulse is generated to have the gate-on voltage in the third step and is generated to have a gate-off voltage in the first, second, fourth and fifth steps,
the second scan pulse is generated to have the gate-on voltage in the first and third steps and is generated to have the gate-off voltage in the second, fourth and fifth steps, the first light-emitting control pulse is generated to have the gate-off voltage in the second and third steps and is generated to have the gate-on voltage in the first, fourth and fifth steps,
the second light-emitting control pulse is generated to have the gate-off voltage in the second, third and fourth steps and is generated to have the gate-on voltage in the first and fifth steps, and
the first, second, third, fourth and fifth switch elements are turned on by the gate-on voltage and turned off by the gate-off voltage.
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