| CPC G09G 3/3266 (2013.01) [G11C 19/28 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0286 (2013.01)] | 17 Claims |
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1. A display substrate, comprising:
a base substrate, comprising a pixel array region and a peripheral region,
a gate driving circuit, a plurality of power lines, a first signal line group, and a second signal line group, in the peripheral region and on at least one side of the base substrate,
wherein the gate driving circuit comprises a plurality of cascaded shift register units;
the plurality of power lines are configured to provide a plurality of power signals to the plurality of cascaded shift register units comprised in the gate driving circuit;
the first signal line group comprises at least one clock signal line, and the at least one clock signal line is configured to provide at least one clock signal to the plurality of cascaded shift register units comprised in the gate driving circuit;
the second signal line group comprises a trigger signal line, and the trigger signal line is configured to be connected to a first-stage shift register unit in the plurality of cascaded shift register units comprised in the gate driving circuit to provide a trigger signal to the first-stage shift register unit;
the gate driving circuit comprises at least one transistor, an extending direction of a channel of the at least one transistor is parallel to an extending direction of the at least one clock signal line, and the extending direction of the at least one clock signal line is a second direction;
the at least one clock signal comprises a first clock signal, the plurality of power signals comprise a first power signal, each of the plurality of cascaded shift register units comprises an input control circuit, an output circuit, and an input circuit, the input control circuit is configured to input the first power signal to the output circuit in response to the first clock signal, and the input circuit is configured to input an input signal to the output circuit in response to the first clock signal;
each of the plurality of cascaded shift register units further comprises an output terminal, the at least one clock signal further comprises a second clock signal, the plurality of power signals further comprise a second power signal, the output terminal is electrically connected to the output circuit, and the output circuit is configured to output the second clock signal or the second power signal to the output terminal under control of the input signal and the first power signal;
the at least one clock signal line comprises a first clock signal line providing the first clock signal and a second clock signal line providing the second clock signal, and the plurality of power lines comprise a first power line providing the first power signal and a second power line providing the second power signal;
the output circuit comprises an output sub-circuit, a first output control sub-circuit, and a second output control sub-circuit;
the output sub-circuit is electrically connected to the second clock signal line, the output terminal, and a first node, respectively, and the output sub-circuit is configured to output the second clock signal on the second clock signal line to the output terminal under control of a level of the first node;
the first output control sub-circuit is electrically connected to the second power line, the output terminal, and a second node, respectively, and the first output control sub-circuit is configured to output the second power signal on the second power line to the output terminal under control of a level of the second node;
the second output control sub-circuit is electrically connected to the first node, the second node, a third node, the first clock signal line, the second clock signal line, the first power line, and the second power line, respectively, and the second output control sub-circuit is configured to control the level of the first node and the level of the second node;
the input control circuit is electrically connected to the second node and is configured to write the first power signal on the first power line to the second node under control of the first clock signal on the first clock signal line; and
the input circuit is electrically connected to the third node and is configured to write the input signal to the third node under control of the first clock signal on the first clock signal line.
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