CPC G06T 5/007 (2013.01) [H04N 19/186 (2014.11); H04N 19/60 (2014.11); G06T 2207/10016 (2013.01); G06T 2207/10024 (2013.01)] | 17 Claims |
1. A high dynamic range video decoder circuit comprising:
a dynamic range optimizer circuit, wherein the dynamic range optimizer circuit comprises a luma mapper and a range stretcher,
wherein the luma mapper is arranged to apply a first luma mapping to an input pixel luma of an input image yielding an intermediate pixel luma,
wherein the range stretcher is arranged to map the intermediate pixel luma to an offset when the value of the intermediate pixel luma is zero yielding a first luma; and
a gain limiter,
wherein the gain limiter is arranged to apply a second luma mapping to the input pixel luma,
wherein the second luma mapping is applied to the input image luma to obtain a second luma,
wherein the gain limiter is arranged to select as output luma the smaller one of the first luma and the second luma.
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