US 11,886,931 B2
Inter-node execution of configuration files on reconfigurable processors using network interface controller (NIC) buffers
Ram Sivaramakrishnan, San Jose, CA (US); Sumti Jairath, Santa Clara, CA (US); Emre Ali Burhan, Sunnyvale, CA (US); Manish K. Shah, Austin, TX (US); Raghu Prabhakar, San Jose, CA (US); Ravinder Kumar, Fremont, CA (US); Arnav Goel, San Jose, CA (US); Ranen Chatterjee, Fremont, CA (US); Gregory Frederick Grohoski, Bee Cave, TX (US); Kin Hing Leung, Cupertino, CA (US); Dawei Huang, San Diego, CA (US); Manoj Unnikrishnan, Saratoga, CA (US); Martin Russell Raumann, San Leandro, CA (US); and Bandish B. Shah, San Francisco, CA (US)
Assigned to SambaNova Systems, Inc., Palo Alto, CA (US)
Filed by SambaNova Systems, Inc., Palo Alto, CA (US)
Filed on Nov. 9, 2021, as Appl. No. 17/522,694.
Application 17/522,694 is a continuation of application No. 17/127,929, filed on Dec. 18, 2020, granted, now 11,182,221.
Prior Publication US 2022/0197713 A1, Jun. 23, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/50 (2006.01); G06F 9/455 (2018.01)
CPC G06F 9/5077 (2013.01) [G06F 9/45558 (2013.01); G06F 9/5027 (2013.01); G06F 2009/4557 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A data processing system, comprising:
a first reconfigurable processor operatively coupled to a first host processor running on a first processing node;
a second reconfigurable processor operatively coupled to a second host processor on a second processing node;
a first Network Interface Controller (NIC) operatively coupled to the first processing node, the first NIC having a first plurality of buffers;
a second NIC operatively coupled to the second processing node, the second NIC having a second plurality of buffers; and
runtime logic configured to execute configuration files that define applications and application data for the applications using the first reconfigurable processor and the second reconfigurable processor, the execution including:
the first reconfigurable processor configured to push input data for the applications to one or more buffers in the first plurality of buffers;
the first host processor configured to cause the first NIC to stream the input data to one or more buffers in the second plurality of buffers from the first plurality of buffers; and
the second host processor configured to cause the second NIC to stream the input data to the second reconfigurable processor from the buffers in the second plurality of buffers;
wherein the second host processor uses one or more Remote Direct Memory Access (RDMA) commands to update tail pointers of the buffers in the second plurality of buffers after the input data is streamed to the buffers in the second plurality of buffers; and
wherein the second reconfigurable processor is configured to pull the input data from the buffers in the second plurality of buffers in response to the updated tail pointers.