US 11,886,930 B2
Runtime execution of functions across reconfigurable processor
Ram Sivaramakrishnan, San Jose, CA (US); Sumti Jairath, Santa Clara, CA (US); Emre Ali Burhan, Sunnyvale, CA (US); Manish K. Shah, Austin, TX (US); Raghu Prabhakar, San Jose, CA (US); Ravinder Kumar, Fremont, CA (US); Arnav Goel, San Jose, CA (US); Ranen Chatterjee, Fremont, CA (US); Gregory Frederick Grohoski, Bee Cave, TX (US); Kin Hing Leung, Cupertino, CA (US); Dawei Huang, San Diego, CA (US); Manoj Unnikrishnan, Saratoga, CA (US); Martin Russell Raumann, San Leandro, CA (US); and Bandish B. Shah, San Francisco, CA (US)
Assigned to SambaNova Systems, Inc., Palo Alto, CA (US)
Filed by SambaNova Systems, Inc., Palo Alto, CA (US)
Filed on Nov. 9, 2021, as Appl. No. 17/522,672.
Application 17/522,672 is a continuation of application No. 17/127,929, filed on Dec. 18, 2020, granted, now 11,182,221.
Prior Publication US 2022/0197711 A1, Jun. 23, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/50 (2006.01); G06F 9/455 (2018.01)
CPC G06F 9/5077 (2013.01) [G06F 9/45558 (2013.01); G06F 9/5027 (2013.01); G06F 2009/4557 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A data processing system, comprising:
a plurality of reconfigurable processors including a first reconfigurable processor operatively coupled to a first processing node and additional reconfigurable processors operatively coupled to a second processing node;
wherein the first reconfigurable processor and the additional reconfigurable processors are operatively coupled to different processing nodes;
a plurality of buffers, buffers in the plurality of buffers including first reconfigurable processor-to-additional reconfigurable processors buffers configured to receive data from the first reconfigurable processor and provide the data to the additional reconfigurable processors, and additional reconfigurable processors-to-first reconfigurable processor buffers configured to receive data from the additional reconfigurable processors and provide the data to the first reconfigurable processor;
runtime logic configured to load one or more configuration files for applications on the first reconfigurable processor for execution, the configuration files including a plurality of functions; and
the runtime logic configured to execute a first set of functions in the plurality of functions and data therefor on the first reconfigurable processor, and a second set of functions in the plurality of functions and data therefor on the additional reconfigurable processors,
wherein functions in the second set of functions and the data therefor are transmitted to the additional reconfigurable processors using one or more of the first reconfigurable processor-to-additional reconfigurable processors buffers,
wherein results of executing the functions and the data therefor on the additional reconfigurable processors are transmitted to the first reconfigurable processor using one or more of the additional reconfigurable processors-to-first reconfigurable processor buffers, and
wherein the first reconfigurable processor-to-additional reconfigurable processors buffers operate in a memory of a first smart Network Interface Controller (SmartNIC) operatively coupled to the first processing node, and the additional reconfigurable processors-to-first reconfigurable processor buffers operate in a memory of a second SmartNIC operatively coupled to the second processing node.