CPC G06F 9/5027 (2013.01) [G06F 9/4812 (2013.01); G06F 9/4881 (2013.01); G06F 9/542 (2013.01); G06F 15/8038 (2013.01)] | 18 Claims |
1. A processor comprising:
a plurality of cores; and
one or more interconnects to couple the plurality of cores to memory;
wherein in response to a core configuration command to deactivate a core of the plurality of cores, a region within the memory is updated with an indication of deactivation of the core, and
wherein an interrupt is generated to indicate that the region within the memory is updated with the indication of deactivation of the core.
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