US 11,886,918 B2
Apparatus and method for dynamic control of microprocessor configuration
Ankush Varma, Portland, OR (US); Nikhil Gupta, Portland, OR (US); Vasudevan Srinivasan, Portland, OR (US); Krishnakanth Sistla, Portland, OR (US); Nilanjan Palit, Northborough, MA (US); Abhinav Karhu, Hillsboro, OR (US); Eugene Gorbatov, Hillsboro, OR (US); and Eliezer Weissmann, Haifa (IL)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by INTEL CORPORATION, Santa Clara, CA (US)
Filed on Apr. 11, 2022, as Appl. No. 17/717,859.
Application 17/717,859 is a continuation of application No. 16/833,595, filed on Mar. 28, 2020, granted, now 11,301,298.
Prior Publication US 2022/0244996 A1, Aug. 4, 2022
Int. Cl. G06F 9/50 (2006.01); G06F 9/48 (2006.01); G06F 9/54 (2006.01); G06F 15/80 (2006.01)
CPC G06F 9/5027 (2013.01) [G06F 9/4812 (2013.01); G06F 9/4881 (2013.01); G06F 9/542 (2013.01); G06F 15/8038 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A processor comprising:
a plurality of cores; and
one or more interconnects to couple the plurality of cores to memory;
wherein in response to a core configuration command to deactivate a core of the plurality of cores, a region within the memory is updated with an indication of deactivation of the core, and
wherein an interrupt is generated to indicate that the region within the memory is updated with the indication of deactivation of the core.