US 11,886,882 B2
Pipelines for secure multithread execution
Shubhendu Sekhar Mukherjee, Southborough, MA (US)
Assigned to Marvell Asia Pte, Ltd., Singapore (SG)
Filed by Marvell Asia Pte, Ltd., Singapore (SG)
Filed on Apr. 5, 2022, as Appl. No. 17/713,744.
Application 17/713,744 is a continuation of application No. 17/081,074, filed on Oct. 27, 2020, granted, now 11,372,647.
Claims priority of provisional application 62/944,243, filed on Dec. 5, 2019.
Prior Publication US 2022/0229667 A1, Jul. 21, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/38 (2018.01); H04L 9/06 (2006.01); G06F 9/48 (2006.01)
CPC G06F 9/3836 (2013.01) [G06F 9/485 (2013.01); H04L 9/0631 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An integrated circuit for executing instructions, comprising:
a processor pipeline configured to execute instructions from two or more threads in parallel using execution units of the processor pipeline; and
a thread hazard circuitry configured to
detect that a first instruction of a first thread has been dispatched into a pipeline stage of the processor pipeline,
responsive to detection of dispatch of the first instruction, block instructions of threads other than the first thread from being dispatched into one or more predetermined pipeline stages of the processor pipeline while the first instruction is being executed by an execution unit in at least one of the one or more predetermined pipeline stages of the processor pipeline and while one or more of the instructions of threads other than the first thread remain in the processor pipeline, and
responsive to completion of execution of the first instruction, enable dispatch of instructions of threads other than the first thread into the one or more predetermined pipeline stages of the processor pipeline.