CPC G06F 9/30043 (2013.01) [G06F 9/30101 (2013.01); G06F 9/3806 (2013.01); G06F 12/0238 (2013.01); G06F 2212/7201 (2013.01)] | 20 Claims |
1. A processor comprising:
a plurality of data memories configured to store data operands for the processor, wherein a given one of the plurality of data memories includes a respective range of multiple addressable memory locations; and
an execution circuit coupled to the plurality of data memories, wherein:
the execution circuit is configured to execute instructions defined by an instruction set architecture (ISA) implemented by the processor;
at least one of the instructions defined by the ISA specifies at least one operand stored in a particular one of the plurality of data memories by specifying a first virtual memory select value for selecting the particular one of the plurality of data memories and an address within the particular one of the plurality of data memories;
the execution circuit includes a memory select register that is configured to store a programmable mapping of respective virtual memory select values to respective physical memory select values for the plurality of data memories; and
the execution circuit is configured to map the first virtual memory select value to a first physical memory select value corresponding to the particular one of the plurality of data memories and to access the particular one of the plurality of data memories to access the at least one operand.
|