US 11,886,874 B2
Arithmetic operation device and arithmetic operation method
Tadashi Kishimoto, Tokyo (JP); Goichi Ono, Tokyo (JP); Akira Kitayama, Tokyo (JP); and Daichi Murata, Tokyo (JP)
Assigned to HITACHI ASTEMO, LTD., Hitachinaka (JP)
Appl. No. 17/610,251
Filed by HITACHI ASTEMO, LTD., Hitachinaka (JP)
PCT Filed Apr. 8, 2020, PCT No. PCT/JP2020/015878
§ 371(c)(1), (2) Date Nov. 10, 2021,
PCT Pub. No. WO2020/230488, PCT Pub. Date Nov. 19, 2020.
Claims priority of application No. 2019-092626 (JP), filed on May 16, 2019.
Prior Publication US 2022/0236985 A1, Jul. 28, 2022
Int. Cl. G06F 9/30 (2018.01); G06F 7/499 (2006.01); G06N 3/063 (2023.01)
CPC G06F 9/3001 (2013.01) [G06F 7/4991 (2013.01); G06F 7/49947 (2013.01); G06N 3/063 (2013.01)] 10 Claims
OG exemplary drawing
 
1. An arithmetic operation device that causes a convolution arithmetic unit to perform a convolution arithmetic operation between a filter and target data corresponding to a size of the filter in each of a plurality of convolution layers constituting a neural network, the arithmetic operation device comprising:
a bit reduction unit that reduces a bit string corresponding to a first bit number from a least significant bit of the target data and reduces a bit string corresponding to a second bit number from a least significant bit of a weight that is an element of the filter for each convolution layer; and
a bit addition unit that adds a bit string corresponding to a third bit number obtained by adding the first bit number and the second bit number to a least significant bit of a convolution arithmetic operation result output from the convolution arithmetic unit by inputting the target data and the weight after being reduced by the bit reduction unit to the convolution arithmetic unit.