US 11,886,854 B1
Acceleration-ready program development and deployment for computer systems and hardware acceleration
Pongstorn Maidee, San Jose, CA (US)
Assigned to Xilinx, Inc., San Jose, CA (US)
Filed by Xilinx, Inc., San Jose, CA (US)
Filed on Jun. 30, 2021, as Appl. No. 17/363,920.
Int. Cl. G06F 8/61 (2018.01); G06F 9/448 (2018.01); G06F 9/445 (2018.01)
CPC G06F 8/61 (2013.01) [G06F 9/4494 (2018.02); G06F 9/44521 (2013.01); G06F 9/44536 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method, comprising:
providing a software library having a plurality of functions having compute identifiers;
wherein the software library is associated with a hardware library including one or more hardware accelerated functions, wherein the hardware accelerated functions are associated with the compute identifiers, and each hardware accelerated function is a functional equivalent of a function of the software library having the same compute identifier; and
providing a hybrid executor layer that, when executed by a data processing system with an acceleration-ready computer program built using the software library, is configured to initiate execution of a selected function of the acceleration-ready computer program using a processor of the data processing system or invoke a selected hardware accelerated function of the hardware library having a compute identifier matching the compute identifier of the selected function based on comparing acceleration criteria with acceleration rules;
wherein the comparing includes determining that the selected function has a compute identifier, determining that the selected hardware accelerated function has a compute identifier matching the compute identifier of the selected function, and determining an amount of time required to load the selected hardware accelerated function in a hardware accelerator.