US 11,886,835 B2
Cascade multiplier using unit element analog multiplier-accumulator
Ryan Boesch, Louisville, CO (US); Martin Kraemer, Mountain View, CA (US); and Wei Xiong, Mountain View, CA (US)
Assigned to Ceremorphic, Inc., San Jose, CA (US)
Filed by Redpine Signals, Inc., San Jose, CA (US)
Filed on Dec. 31, 2020, as Appl. No. 17/139,242.
Prior Publication US 2022/0206753 A1, Jun. 30, 2022
Int. Cl. G06F 7/544 (2006.01); H03M 1/12 (2006.01)
CPC G06F 7/5443 (2013.01) [H03M 1/12 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A multi-stage multiplier operative to multiply a digital A input and a digital B input, each A input and B input having n input bits, the multi-stage multiplier comprising:
an input splitter subdividing the n A input bits and B input bits into at least two groups of subdivided bits, each group of subdivided bits having fewer than n bits and coupled to a respective sub-product multiplier generating a digital sub-product value, each sub-product multiplier comprising:
a plurality of unit elements, each said unit element comprising a plurality of AND-groups, each plurality of AND-groups comprising AND gates, each AND gate having one input coupled to a unique one of the subdivided A bits of a respective group and the other AND gate inputs commonly coupled to one of the B bits of the respective group, the output of each AND gate of each AND-group coupled to a particular analog charge line through a charge transfer capacitor of value C, each analog charge line coupled to a first terminal of a respective summing capacitor having a value which as a capacitance value Cs2n where n is a bit weighted order of the respective analog charge line and Cs is a value smaller than C, each summing capacitor having a second terminal which is coupled together with other summing capacitor second terminals and also coupled to an input of an analog to digital converter (ADC) generating a digital value as the output of the sub-multiplier;
each sub-multiplier output coupled to a binary shifter according to an order of the bits of the sub-multiplier;
each binary shifter outputs summed together to form an output.