US 11,886,740 B2
Command prioritization techniques for reducing latency in a memory system
Christopher Joseph Bueb, Folsom, CA (US); and Olivier Duval, Pacifica, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 1, 2021, as Appl. No. 17/457,202.
Prior Publication US 2023/0176776 A1, Jun. 8, 2023
Int. Cl. G06F 3/06 (2006.01); G06F 9/455 (2018.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0613 (2013.01); G06F 3/0664 (2013.01); G06F 3/0673 (2013.01); G06F 9/45558 (2013.01); G06F 2009/45583 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving, by a host system and from one or more virtual machines associated with the host system, a plurality of commands to access a memory system common to the one or more virtual machines;
storing, in a command queue of the host system associated with the memory system, the plurality of commands and a set of parameters associated with each command of the plurality of commands according to a first order;
arranging, by the host system, the plurality of commands within the command queue from the first order to a second order that is based at least in part on one or more identified patterns of accessing sequential addresses in the plurality of commands; and
transmitting the plurality of commands to the memory system based at least in part on the second order.