US 11,886,721 B2
Method and system for adjusting memory, and semiconductor device
Shu-Liang Ning, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Oct. 26, 2021, as Appl. No. 17/452,339.
Application 17/452,339 is a continuation of application No. PCT/CN2021/106093, filed on Jul. 13, 2021.
Claims priority of application No. 202010879440.4 (CN), filed on Aug. 27, 2020.
Prior Publication US 2022/0066661 A1, Mar. 3, 2022
Int. Cl. G06F 3/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0629 (2013.01) [G06F 3/0614 (2013.01); G06F 3/0653 (2013.01); G06F 3/0673 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method for adjusting a memory, wherein the memory comprises a transistor, a gate of the transistor is electrically connected with a Word Line (WL) of the memory, one of a source and a drain of the transistor is electrically connected with a Bit Line (BL) of the memory, and another one of the source and the drain of the transistor is electrically connected with a storage capacitor of the memory, the method comprising:
acquiring a mapping relationship between a temperature of the transistor, a gate voltage of the transistor, and an actual time at which data is written into the memory;
acquiring a current temperature of the transistor; and
adjusting the gate voltage, based on the current temperature and the mapping relationship, so that the actual time at which the data is written into the memory corresponding to the adjusted gate voltage is within a preset writing time.