US 11,886,712 B2
Die family management on a memory device using block family error avoidance
Steven Michael Kientz, Westminster, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Jul. 1, 2022, as Appl. No. 17/856,771.
Claims priority of provisional application 63/347,918, filed on Jun. 1, 2022.
Prior Publication US 2023/0393745 A1, Dec. 7, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0611 (2013.01) [G06F 3/0653 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
responsive to determining that predetermined number of program erase cycles (PECs) of a memory device has occurred, identifying a target block family of a plurality of block families of the memory device, wherein each block family comprises a plurality of blocks;
obtaining respective temporal voltage shifts of a subset of blocks of the target block family from a plurality of dies associated with the target block family;
obtaining, based on an average of the respective temporal voltage shifts of the subset of blocks, respective die measurements for the plurality of dies; and
assigning, based on the respective die measurements, the plurality of dies to respective die families of a plurality of consecutive die families.