US 11,886,702 B2
Speed bins to support memory compatibility
Eric V. Pohlmann, Boise, ID (US); and Neal J. Koyle, Nampa, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 26, 2022, as Appl. No. 17/585,253.
Claims priority of provisional application 63/145,296, filed on Feb. 3, 2021.
Prior Publication US 2022/0244860 A1, Aug. 4, 2022
Int. Cl. G06F 13/16 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0607 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0683 (2013.01)] 35 Claims
OG exemplary drawing
 
1. A method at a host device, comprising:
reading, by the host device, a value of a register comprising serial presence detect (SPD) data of a first memory module, the SPD data indicative of a timing constraint for operating the first memory module at a corresponding first clock rate, the timing constraint and the corresponding first clock rate associated with a first speed bin;
selecting, for communication with the first memory module, a second speed bin associated with a second clock rate at the host device and the timing constraint, wherein the host device supports operations according to a set of timing constraints that comprises a plurality of values, and wherein the timing constraint is selected from a subset of the set of timing constraints, the subset exclusive of at least one of the plurality of values; and
communicating with the first memory module according to the second speed bin.