US 11,886,362 B2
Gateway processing
Ola Torudbakken, Oslo (NO); and Brian Manula, Stockholm (SE)
Assigned to GRAPHCORE LIMITED, Bristol (GB)
Filed by Graphcore Limited, Bristol (GB)
Filed on May 27, 2021, as Appl. No. 17/332,303.
Application 17/332,303 is a continuation of application No. 16/460,666, filed on Jul. 2, 2019, granted, now 11,119,952.
Claims priority of application No. 1811016 (GB), filed on Jul. 4, 2018; and application No. 1904634 (GB), filed on Apr. 2, 2019.
Prior Publication US 2021/0357340 A1, Nov. 18, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/40 (2006.01); G06F 13/16 (2006.01); G06F 12/0813 (2016.01); G06F 12/0868 (2016.01); G06F 9/38 (2018.01); G06F 9/50 (2006.01); H04L 12/54 (2022.01); H04L 12/70 (2013.01)
CPC G06F 13/1673 (2013.01) [G06F 9/3851 (2013.01); G06F 9/5027 (2013.01); G06F 12/0813 (2013.01); G06F 12/0868 (2013.01); G06F 13/1689 (2013.01); H04L 12/5601 (2013.01); H04L 2012/5618 (2013.01); H04L 2012/5625 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A system comprising:
a subsystem for acting as a work accelerator to a host system; and
a gateway for interfacing the subsystem with the host system and transferring data provided by the host system to the subsystem,
wherein the subsystem comprises at least one processor configured to execute compiled code to i) during a compute phase of the subsystem, process data provided by the host system and ii) during an exchange phase of the subsystem, exchange data with the gateway, wherein the exchange phase is separated from the compute phase by a barrier synchronisation indicated in the compiled code executed by the subsystem; and
wherein the gateway comprises an interface for receiving one or more batches of data provided by the host system for transfer to the subsystem during the exchange phase;
wherein the gateway is associated with processing circuitry configured to:
in advance of the barrier synchronisation, perform data preparation processing on the one or more batches of data to produce a first set of prepared data; and
cause said first set of prepared data to be stored in at least one memory of the gateway so as to be available to be transferred to the subsystem during the exchange phase, which follows the barrier synchronisation,
wherein the gateway further comprises a gateway interface for connection to a second gateway, wherein the processing circuitry is further configured to:
process the one or more batches of data to produce a plurality of sets of data; and
apply data preparation operations to at least some of the plurality of sets of data with different settings applied for different ones of the plurality of sets of data to produce a plurality of sets of prepared data, the plurality of sets of prepared data including the first set of prepared data and a second set of prepared data,
wherein the gateway interface is configured to transfer the second set of prepared data to the second gateway.