US 11,886,361 B2
Memory controller and operating method thereof
Young Jo Kim, Gyeonggi-do (KR); and Sung Yeob Cho, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Sep. 9, 2019, as Appl. No. 16/564,898.
Claims priority of application No. 10-2019-0012845 (KR), filed on Jan. 31, 2019.
Prior Publication US 2020/0250113 A1, Aug. 6, 2020
Int. Cl. G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 12/02 (2006.01); G06F 3/06 (2006.01)
CPC G06F 13/1673 (2013.01) [G06F 3/061 (2013.01); G06F 3/064 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G06F 13/404 (2013.01); G06F 2212/7201 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A memory controller for controlling a memory device in response to a read request from a host, the memory controller comprising:
a buffer memory;
a map data controller;
a map data receiver configured to communicate with the memory device; and
a processor configured to receive the read request, and to control the map data receiver to, receive a plurality of mapping entries included in map data read from the memory device, transfer the plurality of mapping entries to both the buffer memory and the map data controller, and provide a requested logical block address corresponding to the read request to the map data controller,
wherein the map data controller, concurrently with the plurality of mapping entries being transferred to the buffer memory, is configured to detect a mapping entry of the requested logical block address among the plurality of mapping entries, and to output an interrupt signal to the processor in response to detection of the mapping entry of the requested logical block address.