US 11,886,348 B2
Interleaved cache prefetching
Laurent Isenegger, Morgan Hill, CA (US); Robert M. Walker, Raleigh, NC (US); and Cagdas Dirik, Indianola, WA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 6, 2023, as Appl. No. 18/117,820.
Application 18/117,820 is a continuation of application No. 17/464,563, filed on Sep. 1, 2021, granted, now 11,599,472.
Prior Publication US 2023/0205701 A1, Jun. 29, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 12/0862 (2016.01); G06F 12/0831 (2016.01)
CPC G06F 12/0862 (2013.01) [G06F 3/061 (2013.01); G06F 3/0658 (2013.01); G06F 3/0683 (2013.01); G06F 12/0835 (2013.01); G06F 2212/283 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
tracking, at a direct memory access (DMA) controller of a memory device, which source addresses are accessed by which cache controllers of a number of cache controllers;
detecting access patterns of the number of cache controllers based on the tracked source addresses;
anticipating future source address access based on the detected access patterns by prefetching associated data into a local buffer in the memory device; and
sending prefetched data from a first cache controller of the number of cache controllers to a second cache controller of the number of cache controllers based on the anticipated future source address access.