US 11,886,346 B2
Cache read context switching in a memory sub-system
Giuseppe D'Eliseo, Avezzano (IT); Anna Scalesse, Avezzano (IT); Umberto Siciliani, Rubano (IT); and Carminantonio Manganelli, Avezzano (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 22, 2021, as Appl. No. 17/302,067.
Prior Publication US 2022/0342823 A1, Oct. 27, 2022
Int. Cl. G06F 12/00 (2006.01); G06F 12/0844 (2016.01); G06F 3/06 (2006.01)
CPC G06F 12/0844 (2013.01) [G06F 3/0659 (2013.01); G06F 2212/1021 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array configured with a plurality of memory planes; and
control logic, operatively coupled with the memory array, to perform operations comprising:
receiving, from a requestor, a plurality of cache read commands requesting first data from the memory array spread across the plurality of memory planes;
receiving, from the requestor, a cache read context switch command and a snap read command requesting second data from a single plane of the plurality of memory planes of the memory array, wherein the cache read context switch command and the snap read command are stored in a command queue associated with the requestor with an indication of a higher priority than the plurality of cache read commands;
responsive to receiving the cache read context switch command, suspending processing of the plurality of cache read commands; and
processing the snap read command to read the second data from the single plane of the plurality of memory planes of the memory array and return the second data to the requestor.