US 11,886,344 B2
Cached system for managing state vectors
Noel J. Brady, Dublin (IE); and Lars-Olof B Svensson, Stockholm (SE)
Assigned to Xilinx, Inc., San Jose, CA (US)
Filed by Xilinx, Inc., San Jose, CA (US)
Filed on Jun. 29, 2022, as Appl. No. 17/809,833.
Prior Publication US 2024/0004794 A1, Jan. 4, 2024
Int. Cl. G06F 12/0815 (2016.01); G06F 9/30 (2018.01)
CPC G06F 12/0815 (2013.01) [G06F 9/3004 (2013.01); G06F 2212/1021 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A system, comprising:
a cache system including:
a computational cache configured to cache state vectors and perform read-modify-write (RMW) operations on the cached state vectors responsive to received RMW commands; and
a computational cache miss-handler configured to perform RMW operations on state vectors stored in a memory responsive to cache misses in the computational cache, wherein the memory is external to the cache system;
wherein the computational cache miss-handler includes a thread assignment circuit configured to assign the RMW commands corresponding to cache misses to threads and an RMW coalescing circuit configured to combine selected RMW commands belonging to a same thread and having a same index into a single RMW command.