US 11,886,341 B2
Enhancement for activation and deactivation of memory address regions
Nicola Colella, Capodrise (IT); Antonino Pollio, Vico Equense (IT); and Hua Tan, Shanghai (CN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 27, 2022, as Appl. No. 17/850,584.
Application 17/850,584 is a continuation of application No. 16/952,813, filed on Nov. 19, 2020, granted, now 11,379,367.
Prior Publication US 2022/0405205 A1, Dec. 22, 2022
Int. Cl. G06F 12/00 (2006.01); G06F 12/0802 (2016.01); G06F 12/02 (2006.01)
CPC G06F 12/0802 (2013.01) [G06F 12/0223 (2013.01); G06F 2212/604 (2013.01); G06F 2212/608 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory system comprising memory configured as a first cache, the first cache comprising a plurality of entries; and
a controller coupled with the memory system, wherein the controller is configured to:
remove an entry from the first cache based at least in part on receiving a read request, wherein the entry is configured to store a mapping between logical addresses and physical addresses for a respective region of the memory system;
store, to a second cache of the memory system, an index associated with the entry removed from the first cache, wherein the index identifies a region of the memory system associated with the entry removed from the first cache; and
transmit a mapping of the region associated with the entry removed from the first cache based at least in part on storing the index to the second cache of the memory system.