US 11,886,292 B2
Memory system
Kangling Ji, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Appl. No. 17/627,013
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
PCT Filed Aug. 16, 2021, PCT No. PCT/CN2021/112699
§ 371(c)(1), (2) Date Jan. 13, 2022,
PCT Pub. No. WO2022/151730, PCT Pub. Date Jul. 21, 2022.
Claims priority of application No. 202110050737.4 (CN), filed on Jan. 14, 2021.
Prior Publication US 2022/0365844 A1, Nov. 17, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H03M 13/27 (2006.01); H04L 27/34 (2006.01); H04L 1/00 (2006.01); H03M 13/25 (2006.01); G06F 11/10 (2006.01); H03K 19/20 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/1048 (2013.01); H03K 19/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system comprising:
a memory, configured to, during a read or write operation, write or read a plurality of data, wherein the plurality of data are divided into M bytes, each having N data; and
an encoding circuit, configured to generate, at an encoding stage, X first check codes, each based on a subset of the data at fixed bits among all the bytes, and to generate, at the encoding stage, Y second check codes based on all data in a subset of the bytes, wherein the X first check codes are configured for at least one of error detection or error correction on the N data in each of the bytes, and the Y second check codes are configured for at least one of error detection or error correction on the M bytes;
wherein each of M, N, X and Y is a positive natural number.