US 11,886,262 B2
Power management in a multiple-processor computing device
Sau Yan Keith Li, San Jose, CA (US); Thomas E. Dewey, Menlo Park, CA (US); Arthur Chen, Sunnyvale, CA (US); Simon Lai, Mountain View, CA (US); Amit Pabalkar, Fremont, CA (US); and Santosh Nayak, San Jose, CA (US)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on May 3, 2021, as Appl. No. 17/306,654.
Application 17/306,654 is a continuation of application No. 16/108,006, filed on Aug. 21, 2018, granted, now 10,996,725.
Prior Publication US 2021/0255680 A1, Aug. 19, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/00 (2006.01); G06F 1/26 (2006.01); G06F 9/4401 (2018.01); G06F 1/08 (2006.01)
CPC G06F 1/26 (2013.01) [G06F 1/08 (2013.01); G06F 9/4411 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A computer-implemented method for managing power in a multiple processor computing device, the method comprising:
detecting a first amount of power used by one or more non-processor system components of the computing device;
causing one or more other components of the computing device to be put to sleep;
determining a first amount of extra power available based on a difference between the first amount of power and a system power budget associated with the one or more non-processor system components and the one or more other components; and
transmitting, to a driver associated with a first processor included in the computing device, a first value indicating the first amount of extra power available, wherein the driver adjusts at least one operating parameter of the first processor based on the first amount of extra power available.