US 11,884,171 B2
Method and apparatus for minimizing parasitic resistance of output capacitor in LDC
Ji Hoon Park, Suwon-si (KR); Deok Kwan Choi, Yongin-si (KR); Won Gon Kim, Yongin-si (KR); Kang Min Kim, Seoul (KR); Min Heo, Seongnam-si (KR); Tae Ho Bang, Seoul (KR); Du Ho Kim, Yongin-si (KR); Hyun Woo Shim, Suwon-si (KR); Soo Min Jeon, Yongin-si (KR); and A Ra Lee, Seongnam-si (KR)
Assigned to Hyundai Mobis Co., Ltd., Seoul (KR)
Filed by HYUNDAI MOBIS Co., Ltd., Seoul (KR)
Filed on Nov. 22, 2021, as Appl. No. 17/532,525.
Claims priority of application No. 10-2020-0158125 (KR), filed on Nov. 23, 2020.
Prior Publication US 2022/0161672 A1, May 26, 2022
Int. Cl. H02M 3/335 (2006.01); B60L 53/20 (2019.01); B60L 58/20 (2019.01); H02M 1/14 (2006.01); H02M 1/084 (2006.01)
CPC B60L 53/20 (2019.02) [B60L 58/20 (2019.02); H02M 1/084 (2013.01); H02M 1/14 (2013.01); H02M 3/33569 (2013.01); B60L 2210/10 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An apparatus for minimizing a parasitic resistance of an output capacitor of a low-voltage DC-DC converter (LDC), comprising:
an N-phase power circuit configured by connection of N DC-DC converters in parallel between a high-voltage (HV) battery and a low-voltage (LV) battery, in which N is a natural number greater than 1; and
one output capacitor commonly connected to an output of each phase DC-DC converter, wherein each phase of the N-phase power circuit is controlled in an interleaving manner which delays a phase by 360°/N, and
wherein each N-phase power circuit is controlled by switching at a frequency equal to f_im/N, in which f_im is a frequency at which the parasitic resistance of the output capacitor is minimized.