| CPC G11C 16/3481 (2013.01) [G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01)] | 12 Claims |
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1. A memory system, comprising:
a first bit line;
a source line extending in a first direction and a second direction intersecting the first direction;
i-layers, wherein i is an integer equal to or larger than 2, of first word lines adjacent to the source line in a third direction intersecting the first direction and the second direction, the first word lines being stacked in the third direction;
i-layers of second word lines adjacent to the source line in the third direction, the second word lines being stacked in the third direction, positions of i-layers of the second word lines being identical to positions of i-layers of the first word lines in the third direction, respectively;
a first memory pillar between the first word lines and the second word lines, the first memory pillar extending in the third direction, including a first semiconductor layer connected to the first bit line and the source line; and
a control circuit, wherein
the first memory pillar includes a first string provided in a first side of the first memory pillar and a second string provided in a second side of the first memory pillar,
the first string is provided between the first bit line and the source line, and includes a first transistor, a second transistor closer to the source line than the first transistor and i-first memory cells,
the i-first memory cells are provided between the first transistor and the second transistor,
the first transistor, the second transistor, and the i-first memory cells are electrically connected in series,
the i-first memory cells are electrically connected in series, are arranged along the third direction, and are connected to the i-first word lines, respectively,
the second string is provided between the first bit line and the source line, and includes a third transistor, a fourth transistor, and i-second memory cells,
the i-second memory cells are provided between the third transistor and the fourth transistor,
the third transistor, the fourth transistor, and the i-second memory cells are electrically connected in series,
the i-second memory cells are electrically connected in series, are arranged along the third direction, and are connected to the i-second word lines, respectively,
the i-first memory cells and the i-second memory cells share the first semiconductor layer,
the control circuit is configured to
perform a first verify operation to one of the first memory cells and one of the second memory cells corresponding thereto while supplying a first voltage to the source line after a first program operation is performed to the one of the first memory cells and the one of the second memory cells,
perform a second verify operation to the one of the first memory cells while supplying a second voltage to the source line after a second program operation is performed to the one of the first memory cells,
perform a third verify operation to the one of the second memory cells while supplying a third voltage to the source line after a third program operation is performed to the one of the second memory cells, and
perform, in accordance with a request from an external device, a write operation or a read operation to the one of the first memory cells or the one of the second memory cells while supplying a fourth voltage lower than the first voltage, the second voltage and the third voltage to the source line,
the first memory pillar includes a columnar-shaped semiconductor layer including a first part belonging to the first string and a second part belonging to the second string, and
channels of the i-first memory cells and channels of the i-second memory cells share parts of the first memory pillar,
wherein the memory system further comprises:
a second bit line adjacent to the first bit line;
i-layers of third word lines adjacent to the source line in the third direction, the third word lines being stacked in the third direction;
i-layers of fourth word lines adjacent to the source line in the third direction, the fourth word lines being stacked in the third direction, positions of i-layers of the third word lines being identical to positions of i-layers of the fourth word lines in the third direction, respectively; and
a second memory pillar between the third word lines and the fourth word lines, the second memory pillar extending in the third direction, and including a second semiconductor layer connected to the second bit line and the source line, wherein
the second memory pillar includes a third string provided in a third side of the second memory pillar and a fourth string provided in a fourth side of the second memory pillar,
the third string is provided between the second bit line and the source line, and includes a fifth transistor, a sixth transistor, and i-third memory cells,
the i-third memory cells are provided between the fifth transistor and the sixth transistor,
the fifth transistor, the sixth transistor, and the i-third memory cells are electrically connected in series,
the i-third memory cells are electrically connected in series, are arranged along the third direction, and are connected to the i-third word lines, respectively,
the fourth string is provided between the second bit line and the source line, and includes a seventh transistor, an eighth transistor, and i-fourth memory cells,
the i-fourth memory cells are provided between the seventh transistor and the eighth transistor,
the seventh transistor, the eighth transistor, and the i-fourth memory cells are electrically connected in series,
the i-fourth memory cells are electrically connected in series, are arranged along the third direction, and are connected to the i-fourth word lines, respectively,
the i-third memory cells and the i-fourth memory cells share the second semiconductor layer, and
the control circuit is further configured to
boost a voltage of the first bit line by boosting a voltage of the second bit line while maintaining a potential of the first bit line in a floating state, and
perform at least one of the first verify operation, the second verify operation, and the third verify operation.
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