| CPC H10B 12/315 (2023.02) [H10B 12/033 (2023.02); H10B 12/34 (2023.02)] | 17 Claims |
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1. A semiconductor memory device comprising:
a substrate;
a first lower electrode group on the substrate and comprising a plurality of first lower electrodes;
a second lower electrode group on the substrate and comprising a plurality of second lower electrodes;
a first support pattern on side walls of each of the first lower electrodes and connecting each of the first lower electrodes; and
a second support pattern on side walls of each of the second lower electrodes and connecting each of the second lower electrodes,
wherein the plurality of first lower electrodes consists of six first edge lower electrodes arranged at respective vertices of a first hexagonal shape and free of electrodes between the respective vertices of the first hexagonal shape, and one first center lower electrode that is centrally positioned within the first hexagonal shape,
the plurality of second lower electrodes consists of six second edge lower electrodes arranged at respective vertices of a second hexagonal shape and free of electrodes between the respective vertices of the second hexagonal shape, and one second center lower electrode that is centrally positioned within the second hexagonal shape,
the first center lower electrode is spaced apart from each of the first edge lower electrodes, without electrodes therebetween, in first, second, and third directions that are different from each other,
the first support pattern is immediately adjacent to the second support pattern, and
the first center lower electrode is spaced apart from the second center lower electrode in a fourth direction that is different from the first, second, and third directions.
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