CPC H04W 56/001 (2013.01) [H04L 5/001 (2013.01); H04L 5/0048 (2013.01); H04W 4/40 (2018.02); H04W 72/23 (2023.01); H04L 5/0005 (2013.01); H04L 5/0007 (2013.01); H04L 5/0051 (2013.01); H04L 5/0094 (2013.01); H04L 5/0098 (2013.01); H04W 88/02 (2013.01)] | 20 Claims |
1. An apparatus comprising:
memory; and
processing circuitry in communication with the memory, wherein the processing circuitry is configured to:
decode one or more sidelink synchronization signals (SLSSs) received on one or more carriers;
for each of the one or more carriers on which the one or more SLSSs are decoded, determine a priority level for a carrier based on an indicator in one or more respective SLSSs received on the carrier;
select, from the one or more carriers on which one or more SLSSs are decoded, the carrier for which the determined priority level is highest; and
determine a reference timing for sidelink communication based on the one or more SLSSs received on the selected carrier.
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