US 11,882,295 B2
Low-power high throughput hardware decoder with random block access
Nilanjan Goswami, Livermore, CA (US); and Sonal Pinto, Santa Clara, CA (US)
Assigned to Meta Platforms Technologies, LLC, Menlo Park, CA (US)
Filed by META PLATFORMS TECHNOLOGIES, LLC, Menlo Park, CA (US)
Filed on Apr. 15, 2022, as Appl. No. 17/721,687.
Prior Publication US 2023/0336745 A1, Oct. 19, 2023
Int. Cl. H04N 11/02 (2006.01); H04N 19/176 (2014.01); H04N 19/132 (2014.01)
CPC H04N 19/176 (2014.11) [H04N 19/132 (2014.11)] 20 Claims
OG exemplary drawing
 
1. A method comprising, by a computing system:
receiving a block comprising a plurality of pixels;
encoding the plurality of pixels by:
arranging the plurality of pixels in a sequence;
generating a delta encoding of the plurality of pixels, the delta encoding comprising (a) a base value and (b) a plurality of delta values having non-zero delta values and zero delta values, each delta value representing a difference between a corresponding pixel in the sequence and a previous pixel in the sequence;
generating a symbol mask indicating whether each of the plurality of delta values is zero or non-zero;
determining, based on magnitudes of the non-zero delta values, a symbol width for encoding each of the non-zero delta values;
generating a sequence of symbols that respectively encode the non-zero delta values using the symbol width;
generating a compression of the block by collating the symbol mask, the symbol width, and the sequence of symbols.