| CPC H04N 19/119 (2014.11) [H04N 19/176 (2014.11); H04N 19/184 (2014.11); H04N 19/60 (2014.11)] | 5 Claims |
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1. An encoder comprising:
circuitry; and
a memory coupled to the circuitry,
wherein the circuitry, in operation:
determines whether or not a ternary split process of splitting a block into three sub blocks in a first direction parallel to a first longer side of the block is allowed by comparing a size of a second shorter side of the block to a minimum threshold value;
responsive to the ternary split process being allowed, writes, into a bitstream, a split direction parameter indicative of a splitting direction;
splits the block into a plurality of sub blocks in a direction indicated by the split direction parameter;
splits the block into a plurality of sub blocks in a second direction parallel to the second shorter side of the block when the ternary split process is not allowed; and
encodes the plurality of sub blocks.
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