US 11,881,867 B2
Calibration scheme for filling lookup table in an ADC
Narasimhan Rajagopal, Chennai (IN); Eeshan Miglani, Chhindwara (IN); Chirag Chandrahas Shetty, Thane (IN); Neeraj Shrivastava, Bengaluru (IN); Shagun Dusad, Bengaluru (IN); Srinivas Kumar Reddy Naru, Bengaluru (IN); Nithin Gopinath, Bengaluru (IN); Charls Babu, Thrissur (IN); Shivam Srivastava, Jaunpur (IN); Viswanathan Nagarajan, Bengaluru (IN); Jagannathan Venkataraman, Bengaluru (IN); Harshit Moondra, Mumbai (IN); Prasanth K, Kerala (IN); and Visvesvaraya Appala Pentakota, Bengaluru (IN)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Sep. 7, 2021, as Appl. No. 17/467,561.
Claims priority of application No. 202141004382 (IN), filed on Feb. 1, 2021.
Prior Publication US 2022/0247420 A1, Aug. 4, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H03M 1/10 (2006.01)
CPC H03M 1/1019 (2013.01) 22 Claims
OG exemplary drawing
 
1. A circuit comprising:
a calibration engine configured to generate a plurality of input codes;
a digital to analog converter (DAC) coupled to the calibration engine, and configured to generate a first calibration signal in response to a first input code of the plurality of input codes;
an analog to digital converter (ADC) coupled to the DAC and configured to generate a plurality of raw codes responsive to the first calibration signal; and
a storage circuit coupled to the ADC and configured to store a first output code corresponding to the first input code, the first output code is obtained using the plurality of raw codes generated by the ADC.