US 11,881,862 B2
Mitigation of duty-cycle distortion
Udayakiran Kumar Yallamaraju, Bangalore (IN); Xia Li, San Diego, CA (US); Pankaj Deshmukh, San Diego, CA (US); Vajram Ghantasala, San Jose, CA (US); Bin Yang, San Diego, CA (US); Vishal Mishra, Bangalore (IN); Bharatheesha Sudarshan Jagirdar, San Diego, CA (US); Arun Sundaresan Iyer, Bangalore (IN); Amod Phadke, Bangalore (IN); and Vanamali Bhat, Bangalore (IN)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Aug. 17, 2021, as Appl. No. 17/404,919.
Prior Publication US 2023/0058318 A1, Feb. 23, 2023
Int. Cl. H03K 5/156 (2006.01); H03K 5/134 (2014.01); H03K 19/20 (2006.01); H03K 5/00 (2006.01)
CPC H03K 5/1565 (2013.01) [H03K 5/134 (2014.07); H03K 19/20 (2013.01); H03K 2005/00195 (2013.01)] 39 Claims
OG exemplary drawing
 
1. A system, comprising:
a first park circuit having a signal input, an output, and a control input, wherein the first park circuit is configured to couple the signal input of the first park circuit to the output of the first park circuit or to park the output of the first park circuit at a first logic value in response to a first control signal;
a first signal path having an input and an output, wherein the input of the first signal path is coupled to the output of the first park circuit;
a second park circuit having a signal input, an output, and a control input, wherein the signal input of the second park circuit is coupled to the output of the first signal path, wherein the second park circuit is configured to couple the signal input of the second park circuit to the output of the second park circuit or to park the output of the second park circuit at a second logic value in response to a second control signal; and
a second signal path having an input and an output, wherein the input of the second signal path is coupled to the output of the second park circuit.