US 11,881,825 B2
Trimming operational amplifiers
Vadim Valerievich Ivanov, Tucson, AZ (US); Munaf Hussain Shaik, Tucson, AZ (US); Srinivas Kumar Pulijala, Tucson, AZ (US); Patrick Forster, Freising (DE); and Jerry Lee Doorenbos, Tucson, AZ (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Dec. 29, 2020, as Appl. No. 17/136,073.
Prior Publication US 2022/0209730 A1, Jun. 30, 2022
Int. Cl. H03F 3/45 (2006.01); H03M 1/66 (2006.01); H03M 1/38 (2006.01)
CPC H03F 3/45475 (2013.01) [H03M 1/38 (2013.01); H03M 1/66 (2013.01); H03F 2200/375 (2013.01)] 14 Claims
OG exemplary drawing
1. A system comprising:
an operational amplifier (op-amp) with adjustable operational parameters, and a trimming module;
wherein the trimming module adjusts the operational parameters of the op-amp based on a memory value to compensate for an offset voltage of the op-amp;
wherein the trimming module comprises a successive approximation register (SAR) logic that controls the memory value, the SAR logic being configured to detect a given memory value that causes an output voltage of the op-amp to be within a predetermined voltage interval when applying a predetermined common mode voltage to inverting and non-inverting inputs of the op-amp; and
wherein the SAR logic comprises conducting a first number of iterations for determining coarse bits of the memory value and conducting a second number of iterations for determining remaining fine bits of the memory value, wherein the first number of iterations are conducted at a first clock cycle duration, and wherein the second number of iterations are conducted at a second clock cycle duration, the first clock cycle duration being shorter than the second clock cycle duration.