US 11,881,530 B2
Spacer structures for semiconductor devices
Cheng-Yi Peng, Taipei (TW); and Song-Bor Lee, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jan. 24, 2022, as Appl. No. 17/582,860.
Application 17/582,860 is a continuation of application No. 16/807,303, filed on Mar. 3, 2020, granted, now 11,233,149.
Prior Publication US 2022/0149178 A1, May 12, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/417 (2006.01); H01L 29/78 (2006.01); H01L 29/165 (2006.01)
CPC H01L 29/7848 (2013.01) [H01L 29/0665 (2013.01); H01L 29/165 (2013.01); H01L 29/41775 (2013.01); H01L 29/42392 (2013.01); H01L 29/6656 (2013.01); H01L 29/66439 (2013.01); H01L 29/66553 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a stack of nanostructured layers with first and second regions disposed on the substrate;
first and second source/drain (S/D) regions disposed on the substrate;
a gate-all-around (GAA) structure disposed between the first and second S/D regions and around each of the second regions;
inner spacers disposed between the GAA structure and the first and second S/D regions; and
a passivation layer disposed on sidewalls of the first and second regions.