CPC H01L 29/7848 (2013.01) [H01L 29/0665 (2013.01); H01L 29/165 (2013.01); H01L 29/41775 (2013.01); H01L 29/42392 (2013.01); H01L 29/6656 (2013.01); H01L 29/66439 (2013.01); H01L 29/66553 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/0673 (2013.01)] | 20 Claims |
1. A semiconductor device, comprising:
a substrate;
a stack of nanostructured layers with first and second regions disposed on the substrate;
first and second source/drain (S/D) regions disposed on the substrate;
a gate-all-around (GAA) structure disposed between the first and second S/D regions and around each of the second regions;
inner spacers disposed between the GAA structure and the first and second S/D regions; and
a passivation layer disposed on sidewalls of the first and second regions.
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