US 11,881,486 B2
High voltage three-dimensional devices having dielectric liners
Walid M. Hafez, Portland, OR (US); Jeng-Ya D. Yeh, Portland, OR (US); Curtis Tsai, Beaverton, OR (US); Joodong Park, Portland, OR (US); Chia-Hong Jan, Portland, OR (US); and Gopinath Bhimarasetti, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 17, 2023, as Appl. No. 18/111,313.
Application 15/784,318 is a division of application No. 14/975,645, filed on Dec. 18, 2015, granted, now 9,806,095, issued on Oct. 31, 2017.
Application 14/641,117 is a division of application No. 13/536,732, filed on Jun. 28, 2012, granted, now 8,981,481, issued on Mar. 17, 2015.
Application 18/111,313 is a continuation of application No. 17/568,652, filed on Jan. 4, 2022, granted, now 11,610,917.
Application 17/568,652 is a continuation of application No. 17/072,850, filed on Oct. 16, 2020, granted, now 11,251,201, issued on Feb. 15, 2022.
Application 17/072,850 is a continuation of application No. 15/931,881, filed on May 14, 2020, granted, now 10,847,544, issued on Nov. 24, 2020.
Application 15/931,881 is a continuation of application No. 15/946,666, filed on Apr. 5, 2018, granted, now 10,692,888, issued on Jun. 23, 2020.
Application 15/946,666 is a continuation of application No. 15/784,318, filed on Oct. 16, 2017, granted, now 9,972,642, issued on May 15, 2018.
Application 14/975,645 is a continuation of application No. 14/641,117, filed on Mar. 6, 2015, granted, now 9,570,467, issued on Feb. 14, 2017.
Prior Publication US 2023/0207569 A1, Jun. 29, 2023
Int. Cl. H01L 27/12 (2006.01); H01L 21/8234 (2006.01); H01L 21/84 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01)
CPC H01L 27/1211 (2013.01) [H01L 21/0228 (2013.01); H01L 21/02164 (2013.01); H01L 21/02532 (2013.01); H01L 21/02598 (2013.01); H01L 21/28158 (2013.01); H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823462 (2013.01); H01L 21/823468 (2013.01); H01L 21/845 (2013.01); H01L 29/42356 (2013.01); H01L 29/51 (2013.01); H01L 29/513 (2013.01); H01L 29/6656 (2013.01); H01L 29/6681 (2013.01); H01L 29/66545 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating an integrated circuit structure, the method comprising:
forming a high voltage transistor, the forming comprising:
forming a gate electrode over a three-dimensional semiconductor body, the gate electrode having a first side opposite a second side;
forming a first gate dielectric between the three-dimensional semiconductor body of the high voltage transistor and the gate electrode of the high voltage transistor, wherein the first gate dielectric comprises a first high-k dielectric layer, and wherein the first high-k dielectric layer is further along sides of the gate electrode of the high voltage transistor; and
forming a first source or drain region at the first side of the gate electrode; and
forming a second source or drain region at the second side of the gate electrode; and
forming a low voltage transistor, the forming comprising:
forming a gate electrode over a three-dimensional semiconductor body, the gate electrode having a first side opposite a second side;
forming a second gate dielectric between the three-dimensional semiconductor body of the low voltage transistor and the gate electrode of the low voltage transistor, wherein the second gate dielectric comprises a second high-k dielectric layer, and wherein the second high-k dielectric layer is further along sides of the gate electrode of the low voltage transistor; and
forming a first source or drain region at the first side of the gate electrode; and
forming a second source or drain region at the second side of the gate electrode;
forming a first conductive contact on the first source or drain region of the high voltage transistor, the first conductive contact laterally spaced apart from the first side of the gate electrode of the high voltage transistor by a first distance;
forming a second conductive contact on the second source or drain region of the high voltage transistor, the second conductive contact laterally spaced apart from the second side of the gate electrode of the high voltage transistor by approximately the first distance;
forming a third conductive contact on the first source or drain region of the low voltage transistor, the third conductive contact laterally spaced apart from the first side of the gate electrode of the low voltage transistor by a second distance, the second distance less than the first distance; and
forming a fourth conductive contact on the second source or drain region of the low voltage transistor, the fourth conductive contact laterally spaced apart from the second side of the gate electrode of the low voltage transistor by approximately the second distance.