US 11,881,431 B2
Anti-fuse with laterally extended liner
Chanro Park, Clifton Park, NY (US); Koichi Motoyama, Clifton Park, NY (US); Kenneth Chun Kuen Cheng, Shatin (HK); and Chih-Chao Yang, Glenmont, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Nov. 22, 2021, as Appl. No. 17/456,016.
Prior Publication US 2023/0163026 A1, May 25, 2023
Int. Cl. H01L 21/768 (2006.01); H01L 23/525 (2006.01); H01L 23/532 (2006.01)
CPC H01L 21/76829 (2013.01) [H01L 21/7684 (2013.01); H01L 21/76816 (2013.01); H01L 23/5252 (2013.01); H01L 23/53209 (2013.01); H01L 21/76807 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
a low-k dielectric material on top of a substrate;
two adjacent metal lines in the low-k dielectric material, wherein the two adjacent metal lines have a liner; and
a barrier layer contacting the liner and the low-k dielectric material, wherein a portion of the barrier layer extending laterally from each of the two adjacent metal lines embedding into the low-k dielectric material is an anti-fuse.