US 11,881,241 B2
Resistive memory array with localized reference cells
Chandrahasa Reddy Dinnipati, Andhra Pradesh (IN); Ramesh Raghavan, Hyderabad (IN); and Bipul C. Paul, Mechanicville, NY (US)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on Mar. 31, 2022, as Appl. No. 17/709,525.
Prior Publication US 2023/0317130 A1, Oct. 5, 2023
Int. Cl. G11C 11/16 (2006.01); G11C 7/06 (2006.01)
CPC G11C 11/1673 (2013.01) [G11C 7/06 (2013.01); G11C 11/1655 (2013.01); G11C 11/1657 (2013.01); G11C 11/1675 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A structure comprising:
an array of nonvolatile memory cells;
wordlines and bitlines connected to the nonvolatile memory cells;
sense amplifiers connected to the nonvolatile memory cells;
reference cells connected to the sense amplifiers;
a reference bitline connected to the reference cells, wherein the reference bitline is separate from the bitlines; and
a variable resistor connected to the reference cells, wherein each of the reference cells comprises a transistor connected to the variable resistor, one of the wordlines, the reference bitline, and the sense amplifiers.