CPC G11C 11/1673 (2013.01) [G11C 7/06 (2013.01); G11C 11/1655 (2013.01); G11C 11/1657 (2013.01); G11C 11/1675 (2013.01)] | 20 Claims |
1. A structure comprising:
an array of nonvolatile memory cells;
wordlines and bitlines connected to the nonvolatile memory cells;
sense amplifiers connected to the nonvolatile memory cells;
reference cells connected to the sense amplifiers;
a reference bitline connected to the reference cells, wherein the reference bitline is separate from the bitlines; and
a variable resistor connected to the reference cells, wherein each of the reference cells comprises a transistor connected to the variable resistor, one of the wordlines, the reference bitline, and the sense amplifiers.
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