CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0652 (2013.01); G06F 3/0679 (2013.01)] | 10 Claims |
1. A method for operating a memory device, the method comprising:
providing a memory block including at least one source select transistor coupled between a source line and a bit line, a plurality of memory cells, and a drain select transistor;
controlling a source select line coupled to the at least one source select transistor and a plurality of word lines coupled to the plurality of memory cells to be in a floating state; and
after controlling the at least one source select transistor to be in the floating state, applying an erase voltage to the source line and the bit line.
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