US 11,880,333 B2
Peripheral component interconnect (PCI) backplane connectivity system on chip (SoC)
Jason A. T. Jones, Richmond, TX (US); Sriramakrishnan Govindarajan, Bangalore (IN); Mihir Narendra Mody, Bangalore (IN); Kishon Vijay Abraham Israel Vijayponraj, Bangalore (IN); Bradley Douglas Cobb, Sugar Land, TX (US); Sanand Prasad, Plano, TX (US); Gregory Raymond Shurtz, Houston, TX (US); Martin Jeffrey Ambrose, Missouri City, TX (US); and Jayant Thakur, Bangalore (IN)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on May 7, 2021, as Appl. No. 17/314,313.
Application 17/314,313 is a continuation of application No. 16/221,364, filed on Dec. 14, 2018, granted, now 11,030,144.
Prior Publication US 2021/0263883 A1, Aug. 26, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 15/78 (2006.01); G06F 13/10 (2006.01)
CPC G06F 15/7807 (2013.01) [G06F 13/10 (2013.01); G06F 15/7864 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a first function circuit including:
a first plurality of registers, each of which is configured to store an address associated with a memory region of a second circuit; and
a first input address translation unit including a plurality of translation registers, each of which is configured to associate one of the first plurality of registers with a local address that is associated with the second circuit,
wherein the first function circuit is configured to:
receive a first transaction directed to the second circuit, wherein the first transaction is associated with a first address;
determine a first register from the first plurality of registers based on the first address;
determine a first translation register from the plurality of translation registers based on the first register;
determine a first local address associated with the second circuit based on the first translation register of the first input address translation unit; and
transmit the first transaction based on the first local address to the second circuit.