US 11,880,309 B2
Method and system for tracking state of cache lines
Nishchay Dua, Pleasanton, CA (US); Andreas Nowatzyk, San Jose, CA (US); Isam Wadih Akkawi, Santa Clara, CA (US); Pratap Subrahmanyam, Saratoga, CA (US); Venkata Subhash Reddy Peddamallu, Sunnyvale, CA (US); and Adarsh Seethanadi Nayak, San Jose, CA (US)
Assigned to VMware, Inc., Palo Alto, CA (US)
Filed by VMware, Inc., Palo Alto, CA (US)
Filed on Jun. 23, 2021, as Appl. No. 17/355,941.
Prior Publication US 2022/0414017 A1, Dec. 29, 2022
Int. Cl. G06F 12/0897 (2016.01); G06F 12/0831 (2016.01); G06F 12/0862 (2016.01)
CPC G06F 12/0897 (2013.01) [G06F 12/0833 (2013.01); G06F 12/0862 (2013.01); G06F 2212/152 (2013.01)] 18 Claims
OG exemplary drawing
1. A method of tracking state of cache lines that are transferred into and out of one or more caches of processing hardware from and into system memory, the method comprising:
storing a bitmap that indicates the state of the cache lines in the system memory;
monitoring the processing hardware for cache coherence events on a coherence interconnect that is connected between the processing hardware and monitoring hardware;
determining, based on the monitoring, that the state of a cache line has changed from a first state to a second state; and
updating a hierarchical data structure and a cache for the bitmap, both of which are stored in a local memory of the monitoring hardware that is different from the system memory and has a smaller capacity and higher memory access speeds than the system memory, to indicate the change in the state of said cache line from the first state to the second state, wherein
the hierarchical data structure includes a first level data structure including a plurality of first bits, and a second level data structure including a plurality of second bits, each of the first bits associated with a group of the second bits, and
the updating includes setting one of the first bits and one of the second bits in the group corresponding to the first bit that is being set, according to an address of said cache line.