US 11,880,287 B2
Management of microservices failover
Rajesh Poornachandran, Portland, OR (US); Marcos Carranza, Portland, OR (US); Kshitij Arun Doshi, Tempe, AZ (US); Francesc Guim Bernat, Barcelona (ES); and Karthik Kumar, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 7, 2022, as Appl. No. 18/062,950.
Application 18/062,950 is a continuation of application No. 17/560,857, filed on Dec. 23, 2021, granted, now 11,561,868.
Prior Publication US 2023/0205652 A1, Jun. 29, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/00 (2006.01); G06F 11/20 (2006.01)
CPC G06F 11/2025 (2013.01) [G06F 11/2028 (2013.01); G06F 2201/85 (2013.01)] 21 Claims
OG exemplary drawing
1. A system comprising:
a processing resource; and
a machine-readable medium, coupled to the processing resource, having stored therein instructions, which when executed by the processing resource cause the processing resource to:
receive a failover trigger indicative of an uncorrectable error associated with an XPU on which a task of a service is being performed by a primary microservice;
after receipt of the failover trigger, identify a secondary microservice operating in lockstep with the primary microservice; and
direct the secondary microservice to takeover performance of the task based on failover metadata persisted by or on behalf of the primary microservice.