US 11,880,225 B2
Host device, slave device, and data transfer system
Tadashi Ono, Osaka (JP); Isao Kato, Osaka (JP); and Takuji Maeda, Osaka (JP)
Assigned to PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD., Osaka (JP)
Filed by Panasonic Intellectual Property Management Co., Ltd., Osaka (JP)
Filed on Jun. 15, 2022, as Appl. No. 17/841,054.
Application 17/841,054 is a continuation of application No. PCT/JP2021/046255, filed on Dec. 15, 2021.
Claims priority of application No. 2021-022560 (JP), filed on Feb. 16, 2021.
Prior Publication US 2022/0308893 A1, Sep. 29, 2022
Int. Cl. G06F 1/06 (2006.01); G06F 9/4401 (2018.01); G06F 1/3215 (2019.01)
CPC G06F 9/4403 (2013.01) [G06F 1/06 (2013.01); G06F 1/3215 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A host device that is connected to a slave device via at least a power supply line, a clock line, a command line, and a data line,
wherein the host device:
supplies a power to the slave device via the power supply line after being connected to the slave device,
supplies a first clock having a first frequency and a first voltage value to the slave device via the clock line,
drives the command line at a high level to a low level,
stops the supply of the first clock,
supplies a second clock having a second frequency and a second voltage value to the slave device via the clock line in a state where the data line is driven to a low level,
performs, when the data line is driven to a high level within a first predetermined period after the supply of the second clock, tuning for adjusting punching timing by using a plurality of tuning blocks transmitted from the slave device via the data line within a second predetermined period at an interval of at least a third predetermined period,
receives boot data from the slave device via the data line, and
performs activation using the received boot data, and
wherein the third predetermined period is defined by a clock period between data blocks at a time of continuously transmitting the data blocks after activation of the slave device and by a clock period defined by a data structure of a block pattern included in the plurality of tuning blocks.