US 11,879,940 B2
Dynamic generation of ATPG mode signals for testing multipath memory circuit
Wilson Pradeep, Bangalore (IN); and Prakash Narayanan, Bangalore (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jun. 23, 2021, as Appl. No. 17/355,386.
Application 17/355,386 is a continuation of application No. 16/185,629, filed on Nov. 9, 2018, granted, now 11,073,553.
Claims priority of provisional application 62/611,676, filed on Dec. 29, 2017.
Claims priority of provisional application 62/611,704, filed on Dec. 29, 2017.
Prior Publication US 2021/0318378 A1, Oct. 14, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G01R 31/3177 (2006.01); G01R 31/317 (2006.01); G11C 29/56 (2006.01); G06F 11/10 (2006.01); G11C 29/36 (2006.01); G11C 29/42 (2006.01)
CPC G01R 31/3177 (2013.01) [G01R 31/31718 (2013.01); G01R 31/31724 (2013.01); G06F 11/1048 (2013.01); G06F 11/1068 (2013.01); G11C 29/36 (2013.01); G11C 29/42 (2013.01); G11C 29/56004 (2013.01); G11C 2029/3602 (2013.01); G11C 2029/5602 (2013.01)] 16 Claims
OG exemplary drawing
 
15. A method, comprising:
receiving a signal that indicates a number of pulses to test a memory, wherein the memory includes an error checking and correction (ECC) memory array and a data memory array, and the ECC memory array stores an ECC bit that corresponds to data that is stored in the data memory array;
generating an automatic test pattern generator (ATPG) mode signal for a call, the ATPG mode signal indicating whether a first data or a second data is output from a cell; and
selecting between a clocked logic array that receives the first data and a memory array that receives the second data in response to the ATPG mode signal, the ATPG mode signal causes an output from the clocked logic array to be routed from the memory in a first mode and an output of the memory array to be routed from the memory in a second mode.